1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device multilayer design that reduces the area required for the peripheral support circuit portion of the memory device.
The present application is based on Korean Patent Application No. 96-62410 which is incorporated herein by reference for all purposes.
2. Description of the Related Art
A semiconductor memory device generally includes two primary components--the memory cell array itself and the peripheral support circuit having multiple input/output lines for reading data from and writing data to the memory cells. The area of the semiconductor memory circuit dedicated to these two components is roughly equal where each component takes up half of the total circuit area. With the increasing integration of semiconductor memory devices, the area necessary to define a memory cell on a circuit has been considerably reduced by using new cell structure designs and other methods. In contrast, reduction of the peripheral circuit layout has made relatively slow progress. The metal width and metal-metal spacing in the metal wiring layer is not reduced since a markedly stepped surface is formed between the memory cell array and the layout of the peripheral circuit just before the metalizing process during chip fabrication. Therefore, an area occupied by a signal bussing line is a considerable restrictive factor in reducing the area of the peripheral circuit.
FIG. 1 shows a conventional plan view distribution of power lines and signal bussing lines servicing a circuit layer 1 of a peripheral circuit. The region occupied by the circuit layer 1 (which can, for instance, be a decoder circuit, a buffer circuit, etc.) is shown in dashed outline to show the approximate area of the chip required for the circuit layer 1. Such an area is generally referred to herein as the "peripheral circuit layer area." It is to be appreciated that a circuit designer would desire the area required for the entire peripheral circuit to be as close to the area required for the circuit layer 1 as possible.
In FIG. 1, power line layers 2-1 and 2-2 are formed in a layer above the circuit layer 1 in which the peripheral circuit is arranged. An input/output line 3 of the peripheral circuit and a signal bussing layer 4 connected to the input/output line 3 and to the exterior are formed in a region located beside the circuit layer 1.
If a double metal process is used, the input/output line 3 of the peripheral circuit is formed in the first metal layer, and the power line layers 2-1 and 2-2 and the signal bussing layer 4 are formed in the second metal layer which is different from the first metal layer. This design yields the following vertical arrangement: the circuit layer 1 at the lowest layer, then an insulating layer formed on top of the circuit layer 1, then a first metalized layer, then another insulating layer, and then the second metalized layer. Operative layers can be connected to one another via pass-throughs formed in the insulating layer. Since the power line layers 2-1 and 2-2 and the signal bussing layer 4 occupy a nearly constant area irrespective of the degree to which the semiconductor memory device is integrated, they are a restrictive factor in reducing the layout area of the peripheral circuit. Therefore, the arrangement shown in FIG. 1 would not be very useful in reducing the chip "real estate" required for the peripheral control circuit in the semiconductor memory device.
FIG. 2 shows another conventional layout of the power line and signal bussing line of the peripheral circuit. The input/output line 3 of the peripheral circuit and the signal bussing layer 4 connected thereto are formed in circuit layers disposed above the circuit layer 1. The power line layers 2-1 and 2-2 are separately arranged outside the circuit layer 1.
If the double metal process is used, the input/output line 3 of the peripheral circuit is formed in the first metal layer and the signal bussing layer 4 is formed in the second metal layer. Since there is no layout at a lower layer of the power line layers 2-1 and 2-2, the power line layers 2-1 and 2-2 can be separately formed in the first metal layer and the second metal layer. Therefore, the width of the power line layers 2-1 and 2-2 can be reduced by half. Though the area of the peripheral circuit is reduced compared with the layout of FIG. 1, the power line layers 2-1 and 2-2 are still formed outside of the circuit layer 1 in which the peripheral circuit is formed, therefore increasing the total size of the chip.
Accordingly, the need remains for a peripheral circuit design for a memory device having a reduced footprint on the chip.